Machine Learning + Logic Synthesis (II)
- Duration: April 2021 – July 2021.
- This is a programming contest held in the International Workshop on Logic and Synthesis (IWLS) 2021, which extends, in a fairly significant way, the contest from the previous year 2020.
- The goal is to learn multi-output Boolean circuits (in AIG format) for CIFAR-10 image classification.
- For the learned circuits, 3 different size limits are considered: small (≤ 10,000 AIG nodes), medium (≤ 100,000 AIG nodes) and large (≤ 1,000,000 AIG nodes).
- Our Methods [slides | video | source code]:
- To learn a small or medium circuit, we adopt the one-against-one (OAO) approach that construct a multi-class classifier with an ensemble of binary decision trees.
- To learn a large circuit, we train a shallow convolutional neural network (CNN) model with grouped convolutions and quantized weights. The CNN model is then synthesized with sub-adder sharing to reduce the circuit size.
- We were the 2nd place winner (among 5 participating teams) of the contest.
