Po-Chun Chien

Po-Chun Chien

I am a research assistant in SoSy-Lab.

Publications

Compatible Equivalence Checking of X-Valued Circuits

Published in Proceedings of the International Conference on Computer-Aided Design (ICCAD), 2021

This paper presents our winning method of the 2020 ICCAD CAD Contest based on X-value preserving dual-rail encoding and incremental identification of compatible equivalence relation.

Recommended citation: Y.-N. Wang, Y.-R. Luo, P.-C. Chien, P.-L. Wang, H.-R. Wang, W.-H. Lin, J.-H. R. Jiang and C.-Y. R. Huang, "Compatible Equivalence Checking of X-Valued Circuits," in Proc. ICCAD, 2021. To appear.

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization

Published in Proceedings of the Design, Automation and Test in Europe Conference (DATE), 2021

This paper presents learning incompletely-specified functions based on the results of a competition conducted at IWLS 2020.

Recommended citation: S. Rai et al., "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization," in Proc. DATE, 2021.

Time Multiplexing via Circuit Folding

Published in Proceedings of the Design Automation Conference (DAC), 2020

The structural and functional circuit folding methods are proposed to address time multiplexing in multi-FPGA system. These methods may potentially help alleviate the bottleneck of limited inter-chip I/O bandwidth.

Recommended citation: P.-C. Chien and J.-H. R. Jiang, "Time Multiplexing via Circuit Folding," in Proc. DAC, 2020.

Time-Frame Folding: Back to the Sequentiality

Published in Proceedings of the International Conference on Computer-Aided Design (ICCAD), 2019

Time-frame folding is formulated as the reverse operation of time-frame expansion. This method has the ability in circuit size compaction and applications in logic synthesis domains.

Recommended citation: P.-C. Chien and J.-H. R. Jiang, "Time-frame Folding: Back to the Sequentiality," in Proc. ICCAD, 2019.