Time Multiplexing via Circuit Folding
Published in Proceedings of the Design Automation Conference (DAC), 2020
Recommended citation: P.-C. Chien and J.-H. R. Jiang, "Time Multiplexing via Circuit Folding," in Proc. DAC, 2020.
Abstract:
Time multiplexing is an important technique to overcome the bandwidth bottleneck of limited input-output pins in FPGAs. Most prior work tackles the problem from a physical design standpoint to minimize the number of cut nets or Time Division Multiplexing (TDM) ratio through circuit partitioning or routing. In this work, we formulate a new orthogonal approach at the logic level to achieve time multiplexing through structural and functional circuit folding. The new formulation provides a smooth trade-off between bandwidth and throughput. Experiments show the effectiveness of the structural method and improved optimality of the functional method on look-up-table and flip-flop usage.
Click the links to view the paper [IEEE Xplore | ACM DL | PDF], the presentation [slides | video], the source code and the project page.
To cite the paper, you may use the following BibTex entry.
@inproceedings{Chien:DAC:2020,
author = {Po-Chun Chien and Jie-Hong Roland Jiang},
title = {Time Multiplexing via Circuit Folding},
booktitle = {Proc. DAC},
year = {2020},
doi = {10.1109/dac18072.2020.9218552}
}