CV
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Research Interests
- Formal Verification
- Soft/Hard-ware Model Checking
- QBF/SAT solving
- Automata Theory
- Electronic Design Automation (EDA)
- Logic Synthesis & Optimization
- Highl-level Synthesis
- Computation Models
- Machine Learning (ML)
- Decision Tree
- Deep Learning (DL)
- Machine Comprehension
Skills
- Programming
- C/C++
- Python
- VerilogHDL (SystemVerilog)
- MATLAB
- Cadence SKILL
- Language
- Mandarin Chinese (native)
- English (IELTS 7.5, TOEFL 103, GRE 155/170/4.0)
Education
- Ph.D. in Informatics (Computer Science), LMU Munich
- From July 2021.
- A member of SoSy-Lab led by Prof. Dr. Dirk Beyer.
- M.S. in Electroncis Engineering, National Taiwan University (NTU)
- September 2018 – June 2020.
- Major in Electronic Design Automation.
- A member of ALCom Lab led by Prof. Jie-Hong Roland Jiang.
- Overall GPA: 4.22 / 4.30 or 3.96 / 4.0.
- B.S. in Eletrical Engineering, NTU
- September 2015 – June 2018.
- Overall GPA: 4.16 / 4.30 or 3.96 / 4.0 (top 5%).
Awards
Publications
Compatible Equivalence Checking of X-Valued Circuits
Y.-N. Wang, Y.-R. Luo, P.-C. Chien, P.-L. Wang, H.-R. Wang, W.-H. Lin, J.-H. R. Jiang and C.-Y. R. Huang, "Compatible Equivalence Checking of X-Valued Circuits," in Proc. ICCAD, 2021. To appear.
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization
S. Rai et al., "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization," in Proc. DATE, 2021.
Time Multiplexing via Circuit Folding
P.-C. Chien and J.-H. R. Jiang, "Time Multiplexing via Circuit Folding," in Proc. DAC, 2020.
Circuit Folding: From Combinational to Sequential Circuits
P.-C. Chien, "Circuit Folding: From Combinational to Sequential Circuits," Master's Thesis, National Taiwan University, 2020.
Time-Frame Folding: Back to the Sequentiality
P.-C. Chien and J.-H. R. Jiang, "Time-frame Folding: Back to the Sequentiality," in Proc. ICCAD, 2019.
Work Experiences
- Research Assistant (Wissenschaftlicher Mitarbeiter)
- SoSy-Lab of LMU Munich, from July 2021.
- Supervised by Prof. Dr. Dirk Beyer.
- Part of the DFG Research Training Group ConVeY
- Research Assistant
- ALCom Lab of NTU, July – Nov. 2020, April – June 2021.
- Supervised by Prof. Jie-Hong Roland Jiang.
- Extending my graduate research and exploring new topics (link1, link2).
- Teaching Assistant of "Introduction to Electronic Design Automation"
- NTU, March – July 2020.
- Instructed by Prof. Jie-Hong Roland Jiang.
- Teaching Assistant of "Introduction to Electronic Design Automation"
- NTU, March – July 2019.
- Instructed by Prof. Jie-Hong Roland Jiang.
- Teaching Assistant of "Deep Learning for Human Language Processing"
- NTU, September 2018 – January 2019.
- Instructed by Prof. Hung-Yi Lee and Prof. Yun-Nung Chen.
- Teaching Assistant of “Advanced Deep Learning”
- NTU, March – July 2018.
- Instructed by Prof. Hung-Yi Lee and Prof. Yun-Nung Chen.
- Summer Intern
- MediaTek ADCT/PDK Department, July – August 2018.
- Developed an automatic virtual-pin labeler for LVS on analog circuits.
Research Projects
Related Courses
- Verification: SoC Verification, Logic Synthesis & Verification, Algorithms
- EDA: VLSI Testing, Physical Design, Data Structure & Programming
- ML: ML & have it deep and structured, Advanced DL, DL for Human Language Processing
- Others: Advanced Computer Architecture, Digital Signal Processing, Introduction to Cryptography
Personal Traits
- Highly motivated and eager to learn new things.
- Capable of working as an individual as well as in groups.
- Hard-working and good at time management.