Time Multiplexing via Circuit Folding
- Duration: Nov. 2019 – July 2020
- The research manuscript was accepted and published by the DAC 2020.
- This was my second graduate research project and was the extension of the “Time-Frame Folding” project.
- Time multiplexing (TM) is an important technique to overcome the I/O bandwidth bottleneck of FPGAs.
- Our new formulation achieves TM through structural and functional circuit folding at the logic level.
- Experiments show the effectiveness of the proposed structural method and improved optimality of the proposed functional method on look-up-table and flip-flop usage.
- Click the links to view the paper [IEEE Xplore | ACM DL | PDF], the presentation [slides | video] and the source code.
